1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device having a plurality of memory blocks.
2. Description of the Related Art
In semiconductor memory devices, data read from a memory cell array are supplied to an output circuit through a data bus, and are then output to the exterior of the device from the output circuit through output terminals. The data bus generally tends to extend a long distance. When the memory cell array is comprised of a plurality of blocks, and outputs of the blocks are connected in series by the data bus, the length of the data bus becomes extremely lengthy. This results in a delay in signal transmission.
The time delay of data-bus signals is controlled by the capability of the driver that drives the data bus and by a CR time constant of the data bus lines. In order to shorten the time delay of signals, the diver capability may be boosted, or the signal lines may be widened to reduce R (resistance). Further, the intervals between adjacent signal lines may be extended to reduce C (capacitance). There is a limit to a reduction in signal transmission time that is achieved by boosting the driver capability, so that the enlargement of line widths and line intervals may always be necessary. In this case, however, the size of areas used for signal-line layout increases, resulting in an undesirable increase in the chip size.
In order to obviate these problems, Japanese Patent Laid-open No. 58-199490 teaches reducing transmission delays by dividing the data bus by use of relay buffers.
In the Japanese Patent Laid-open No. 58-199490, a plurality of divided data buses corresponding to a plurality of memory blocks are connected one after another by relay buffers. Since the divided data buses corresponding to the memory blocks are connected in series, relay buffers are driven at the position corresponding to the memory block that outputs data, and are also driven at positions located downstream relative to this position. Relay buffers are not driven at positions located upstream relative to this position. In order to achieve this, circuitry for obtaining an OR logic of block address signals is provided, and enables the relay buffers located downstream (i.e., located closer to the output terminals) relative to the stage where data is output.
For such a construction, the circuitry for obtaining an OR logic of address signals and additional address signal lines become necessary, resulting in increases in chip size and current consumption. In memory macros where the array configuration is modified according to specifications, further, the buffer selecting circuit and signal lines need to be modified depending on how many blocks are connected. A single circuit design cannot thus be used for all the different specifications.
Accordingly, there is a need for a semiconductor memory device that can achieve efficient buffer control in terms of chip size and current consumption in a construction where a plurality of data-bus stages are connected in series.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
In order to achieve these and other advantages in accordance with the purpose of the invention, a semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.
In the semiconductor memory device as described above, the relay buffers are provided for the data buses, thereby enhancing data transfer speed without enlarging the line widths and line intervals of the data buses. The semiconductor memory device also utilizes the signals for block activation in order to properly control the activation/deactivation of the relay buffer circuits. This achieves efficient buffer control in terms of chip size and current consumption.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits deactivating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals and otherwise activating the corresponding one of the buffer circuits.
In the semiconductor memory device described above, only the buffer circuit that is situated upstream next to the data outputting memory block is deactivated at the time of data output from the memory block, and the remaining buffer circuits are activated. At times other than the time of data output, all the buffer circuits are kept active. This insures that the data buses do not float even at times other than the time of data output, which prevents through currents from running in the buffer circuits and the like. There is thus no need for information hold circuits or the like for holding the data of the data buses to either HIGH or LOW, thereby making it possible to achieve efficient buffer control in terms of chip size and current consumption.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.